In 2020, the team in Tokyo pursued the study and characterisation of several quantum algorithms, in order to understand their applicability at different points in the data processing chain. One of the problems being addressed is the acceleration of the event-generation process. Event generators (in particular their integration step) are expected to be extremely demanding in terms of computation time, especially for the generation of multi-jet events at the experiments running in future on the High-Luminosity LHC.
In another line of work, we studied different quantum machine-learning models, such as quantum convolutional neural networks, as applied to both classical and quantum data.
With the limited qubit counts, connectivity and coherence times of present quantum computers, quantum circuit optimisation is crucial for making the best use of these devices. In addition to the algorithmic studies outlined above, we have studied a novel circuit-optimisation protocol, composed of two techniques: pattern recognition of repeated sets of gates and reduction of circuit complexity by identifying computational basis states. The developed optimisation protocol demonstrates a significant gate reduction for a quantum algorithm used to simulate parton shower processes.
Current results are very promising. However, they have been obtained using simulations that assume ideal quantum circuits, without taking into account effects such as noise, measurement errors, or limited coherence time. All of these issues can affect quantum hardware significantly, particularly noisy intermediate-scale quantum devices. Our next steps will include a detailed study of strategies for error mitigation.